1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, more specifically to a nonvolatile semiconductor memory device including memory cells arranged therein, each of the memory cells including a diode and a variable resistor connected in series.
2. Description of the Related Art
In recent years, along with a rising level of integration in semiconductor devices, circuit patterns of transistors and the like which configure the semiconductor devices are being increasingly miniaturized. Required in this miniaturization of the patterns is not simply a thinning of line width but also an improvement in dimensional accuracy and positional accuracy of the patterns. This trend applies also to semiconductor memory devices.
Conventionally known and marketed semiconductor memory devices such as DRAM, SRAM, and flash memory each use a MOSFET as a memory cell. Consequently, there is required, accompanying the miniaturization of patterns, an improvement in dimensional accuracy at a rate exceeding a rate of the miniaturization. As a result, a large burden is placed also on the lithography technology for forming these patterns which is a factor contributing to a rise in product cost.
In recent years, resistive memory is attracting attention as a candidate to succeed these kinds of semiconductor memory devices utilizing a MOSFET as a memory cell (refer, for example, to Japanese Unexamined Patent Application Publication (Translation of PCT Application) No. 2005-522045). The resistive memory devices herein include resistive RAM (ReRAM), in a narrow sense, that uses a transition metal oxide as a recording layer and stores its resistance states in a non-volatile manner, as well as Phase Change RAM (PCRAM) that uses chalcogenide or the like as a recording layer to utilize the resistance information of crystalline states (conductors) and amorphous states (insulators).
It is known that the variable resistance elements in resistive memory have two modes of operation. One is to set a high resistance state and a low resistance state by switching the polarity of the applied voltage, which is referred to as “bipolar type”. The other enables the setting of a high resistance state and a low resistance state by controlling the voltage values and the voltage application time, without switching the polarity of the applied voltage, which is referred to as “unipolar type”.
To achieve high-density memory cell arrays, the unipolar type is preferable. This is because that the unipolar type solution enables, without transistors, cell arrays to be configured by superposing variable resistance elements and rectifier elements, such as diodes, on respective intersections between bit lines and word lines. Moreover, large capacity may be achieved without an increase in cell array area by arranging such memory cell arrays laminated in a three-dimensional manner.
In a unipolar type ReRAM, data write to the memory cell is performed by applying a certain voltage to the variable resistance element for a short time. This allows the variable resistance memory cell to change from a high resistance state to a low resistance state. Such the operation for changing the variable resistance element from a high resistance state to a low resistance state is called “a setting operation”.
On the other hand, data erase of the memory cell is performed by applying a certain voltage that is smaller than that in the setting operation, to the variable resistance element having a low resistance state after the setting operation, for a longer time. This allows the variable resistance memory cell to change from a low resistance state to a high resistance state. Such the operation for changing the variable resistance element from a low resistance state to a high resistance state is called “a reset operation”. The memory cell is in a stable state in the high resistance state (the reset state), for example. If the memory cell stores 2-value data, data write thereto is performed by a setting operation that changes the reset state to a low resistance state.
During a reset operation, a large current of 1 μA or more serving as a resetting current must be passed through the memory cells. However in this case, there is a problem that a voltage occurring between memory cells after completion of the reset operation reaches a value extremely close to the setting voltage required in the previously mentioned setting operation, and an operating margin is small. The operating margin being small means it may occur that, after completion of the reset operation, the memory cells once more mistakenly undergo the setting operation, which is undesirable.
Moreover, in conventional resistive memory, there is a problem that a reverse leak current flowing in the transistor during write is not sufficiently reduced, and power consumption is large.